This invention relates to a semiconductor device having a latch-up protection circuit formed on a semiconductor substrate for preventing a latch-up.
Consider a semiconductor device having an internal Complementary Metal Oxide Semiconductor (CMOS) circuit and an electrostatic breakdown protection circuit formed in an input circuit through which an input signal is input to the CMOS circuit. When an excessive voltage such as electrostatic surge, etc. is input from an input line to the CMOS circuit through the electrostatic breakdown protection circuit, the excessive voltage sometimes triggers a latch-up. Therefore, a latch-up protection circuit is formed on the semiconductor substrate for preventing a latch-up from occurring in the CMOS circuit. The latch-up protection circuit typically has an impurity diffusion region which surrounds the electrostatic breakdown protection circuit on a surface of a semiconductor substrate (called surrounding diffusion region hereinafter). The surrounding diffusion region and the electrostatic breakdown protection circuit form a multicollector type of parasitic bipolar transistor. Hence, as shown in the following first comparative example, a part of the surge can be discharged as a collector current from the input line to the surrounding diffusion region. Consequently, the latch-up protection circuit, which reduces a ratio of the surge flowing into the CMOS circuit, prevents the latch-up from occurring in the CMOS circuit.
Now, in a semiconductor device having a CMOS circuit, for example, in a semiconductor memory device represented by a dynamic random access memory (DRAM), a substrate bias is applied to a semiconductor substrate of the semiconductor device in order to ensure optimum working of the CMOS circuit. The semiconductor device usually has a built-in substrate bias generating circuit for generating a substrate bias to be applied to the semiconductor substrate, because the substrate bias is indispensable for the device to function as a semiconductor device and because the built-in substrate bias generating circuit makes the semiconductor device easy to use. The substrate bias generated by the built-in substrate bias generating circuit is applied to the semiconductor substrate through a diffusion region for applying the substrate bias.
However, if the diffusion region and a surrounding diffusion region have the same conductive type and are coupled with each other, the following problems occur. The substrate bias generating circuit is generally supplied with a little current and has much internal impedance as a power source. So, the substrate bias be changed easily when surge flows from an input line into the substrate bias generating circuit through the surrounding diffusion region. Then, as shown in the following comparative case 2, latch-up in the CMOS circuit occurs more often. Consequently, it becomes more difficult to prevent latch-up from occurring if a latch-up protection circuit which works as a prior multicollector type of parasitic bipolar transistor is formed in the semiconductor device with the built-in substrate bias generating circuit. Namely, latch-up tolerance of the semiconductor device deteriorates.
A protection resistor may be formed between an input line and a CMOS circuit in order to delay the surge flow into the CMOS circuit, instead of forming an electrostatic breakdown protection circuit, so as not to form a multicollector type of parasitic bipolar transistor. If a protection resistor is used, protection resistor needs to have a large enough large resistance.
However, the larger the resistance of the protection resistor, the more transmission of an input signal is delayed. So, a protection resistor with large enough resistance can not be formed in a semiconductor device required to be used in high-speed operation. Consequently, for the conventional semiconductor device with the protection resistor, is difficult to obtain enough electrostatic breakdown tolerance.
Hence, for semiconductor device with a substrate bias generating circuit, it is desired not to reduce operation speed and desired to keep the latch-up tolerance and the electrostatic breakdown tolerance.